PhD, Purdue University; 1985
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From 1985-1989, I was Member Group Technical Staff (MGTS) and Section Manager Texas Instruments Inc in the area of semiconductor process and device simulation. Visiting Professor at MIT in 2001 working on inverse modeling to predict doping profiles in devices.
Simulation and modeling subcommittee chairman of premier IEEE conference International Electron Device Meeting (IEDM 2010). Active in IEEE chapters and conferences.
Design, Simulation and fabrication of semiconductor devices. Using simulators, one can functionality of new and novel devices which then can be fabricated with reasonable success. He is a co-recipient of the IEEE Electron Devices Society's 2008 Paul Rappaport Award. Engaged in collaborative research on Predicting scaling trends and fundamental limitations on device performance using existing and newly developed programs and simulators. Modeling and characterization for RF and nanowire devices. Addressing losses in power semiconductor devices using novel device structures such as oxide bypass Vertical Double-diffused MOS (VDMOS) and Lateral DMOS as well as poly flanked LDMOS. Strained silicon devices to enhance performance of ultrashort channel length devices. Novel MOS devices that exhibit very fast turn-on and turn-off with subthreshold swing lower than 60mV/dec Innovative methods to characterize, model and reduce parasitic series resistance in S/D regions of MOSFETs that limits overall performance at short channel lengths.
Design and Fabrication of Transistor with Improved Subthreshold Characteristics Source: ASTAR SERC, Duration: 3 years 2006-2009, Amount : S$827,263, Co-Principal Investigator, PI - Prof. YC Yeo DEVICE SIMULATION FOR RF APPLICATIONS Source: IME-JML, Duration: 3 years 2004-2007, Amount : S$126,000 Principal Investigator Physical Modeling and Simulation of Nano-Scale Electronic Device Phenomena Source: ASTAR SERC, Duration: 3 years 2004-2007, Amount : $ 602,990 Principal Investigator
Liang*, Y C, X Yang, G S Samudra and K P Gan, "Power MOSFET having enhanced breakdown voltage". United States, 2005. (US Patent No. 6,853,033 B2). Samudra*, G S, RAJENDRAN Krishnasamy, C K Lau and M S Zhou, "Process to achieve uniform groove depth in a silicon substrate". United States: patent no. 6,284,606, 2001.
A total of 80 Journal and 103 conference publications. MA, F J, S Rustagi, G S Samudra, H Zhao, N Singh, G Lo and D Kwong, "Modeling of Stress Retarded Thermal Oxidation of Nonplanar Silicon Structures for Realization of Nanoscale Devices". IEEE ELECTRON DEVICE LETTERS, 31, no. 7 (2010): 719 721. Zhao, H, R Kim, A Paul, M Luisier, G Klimeck, F MA, SC Rustagi, G S Samudra, N Singh, GQ Lo and DL Kwong, "Characterization and Modeling of Subfemtofarad Nanowire Capacitance Using the CBCM Technique". IEEE ELECTRON DEVICE LETTERS, 30, no. 5, pp. 526-528 (2009) Zhao, H, S Rustagi, F MA, G S Samudra, N Singh, GQ Lo and DL Kwong, "Charge Based Capacitance Measurement Technique for Nanoscale, Devices: Accuracy Assessment Based on TCAD Simulations". IEEE TRANSACTIONS ON ELECTRON DEVICES, 56, no. 5 (2009): 1157 1160. WONG, H S, LH TAN, L CHAN, GQ LO, G S Samudra and Y C Yeo, "Gate all around quantum wire field effect transistor with dopant segregation at metal semiconductor metal heterostucture". Symp. on VLSI Tech. 2009 (2009): 92 93. MA, F, SC Rustagi, H Zhao, G S Samudra, N Singh, K Budhaaraju, GQ Lo and DL Kwong, "Modeling of Stress retarded Orientation dependent Oxidation: Shape Engineering of Silicon Nanowire Channels". IEDM proceeding (2009): 517 520. Madan, A, G S Samudra and Y C Yeo, "Strain optimization in ultrathin body transistors with silicon germanium source and drain stressors". JOURNAL OF APPLIED PHYSICS, 104, no. 8 (2008): Art. No. 084505. TOH, E H, H G WANG, L. Chan, D. Weeks, M. Bauer, J. Spear, S. G. Thomas, G S Samudra and Y C Yeo, "Co integration of in situ doped silicon carbon source and silicon carbon I region in p channel silicon nanowire impact ionization transistor". IEEE ELECTRON DEVICE LETTERS, 29, no. 7 (2008): 731 733. Zhu, ZG, Gengchiau LIANG, M F Li and G S Samudra, "A pseudopotential method for investigating the surface roughness effect in ultrathin body transistors". JOURNAL OF PHYSICS CONDENSED MATTER, 20, no. 23 (2008): no. 235229. TOH, E H, H G WANG, G S Samudra and Y C Yeo, "Device physics and design of germanium tunneling field effect transistor with source and drain engineering for low power and high performance applications". JOURNAL OF APPLIED PHYSICS, 102 (2008): 104504. TOH, E H, H G WANG, L. Chan, G S Samudra and Y C Yeo, "Device physics and performance optimization of impact ionization MOS transistors formed using a double spacer fabrication process". JAPANESE JOURNAL OF APPLIED PHYSICS, 47, no. 4 (2008): 3077 3080. TOH, E H, H G WANG, L. Chan, D. Sylvester, C H Heng, G S Samudra and Y C Yeo, "Device design and scalability of a double gate tunneling field effect transistor with silicon germanium source". JAPANESE JOURNAL OF APPLIED PHYSICS, 47, no. 4 (2008): 2593 2597. Zhao, H, Y C Yeo, S C Rustagi and G S Samudra, "Analysis of the Effects of Fringing Electric Field on FinFET Device Performance and Structural Optimization Using 3 D Simulation". IEEE TRANSACTIONS ON ELECTRON DEVICES, 55, no. 5 (2008): 1177 1184. Zhu, Z G, T Low, M F Li, W J Fan, P Bai, D KWONG and G S Samudra, " Pseudo potential band structure calculation of InSb ultra thin films and its application to assess the n metal oxide semiconductor transistor performance". SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 23, no. 2 (2008): Art No 025009. WONG, H S, F LIU, K W ANG, S M KOH, T Y A KOH, T LIOW, T P R LEE, E A LIM, W L FANG, M ZHU, L. Chan, N. Balasubramanian, G S Samudra and Y C Yeo, "Selenium co implantation and segregation as a new contact technology for nanoscale SOI N FETs featuring NiSi:C formed on silicon carbon (Si:C) source/drain stressors". Symp. on VLSI Tech. 2008 (2008): 168 169. Zhao, H, S C Rustagi, N Singh, F MA, G S Samudra, K Budhaaraju, S K Manhas, C H Tung, G Q Lo, G Baccarani and D L Kwong, "Sub Femto Farad Capacitance Voltage Characteristics of Single Channel Gate All Around Nano Wire Transistors for Electrical Characterization of Carrier Transport". IEDM2008 (2008): 769 772. Samudra, G S, Y C Yeo, C H Heng, E H Toh and L Yang, "Simulation of material and strain engineering of tunneling field effect transistor with subthreshold swing below 60 mV/decade". Proceeding of SSDM (2008): 868 869. Tsukuba: Japan society of applied physics. (Invited paper) (Solid State Devices and Materials (SSDM), 24 26 Sep 2008, Tsukuba Convention Centre, Tsukuba, Ibaraki, Japan) Samudra, G S, Y CHEN and Y C Liang, "An enabling device technology for future superjunction power integrated circuits". The 39th IEEE Power Electronics Specialists Conference (2008): 3713 3716. TOH, E H, H G WANG, L Chan, GQ Lo, G S Samudra and Y C Yeo, "Strain and materials engineering for the I MOS transistor with an elevated impact ionization region". IEEE TRANSACTIONS ON ELECTRON DEVICES, 54, no. 10 (2007): 2778 2785. Wong, H S, L Chan, G S Samudra* and Y C Yeo, "Sub 0.1 eV Effective Schottky Barrier Height for NiSi on n Type Si (100) Using Antimony Segregation". IEEE ELECTRON DEVICE LETTERS, 28, no. 8 (2007): 703- 705. Chui, KJ, KW Ang, N Balasubramanian, M F Li, G S Samudra and Y C Yeo, "N MOSFET with silicon carbon source/drain for enhancement of carrier transport", IEEE TRANSACTIONS ON ELECTRON DEVICES, 54, no. 2 (2007): 249 256. Toh, E H, G H Wang, G Q Lo, L Chan, G S Samudra and Y C Yeo, "Performance enhancement of n channel impact ionization metal oxide semiconductor transistor by strain engineering". APPLIED PHYSICS LETTERS, 90, no. 2 (2007). Chen, Y, Y C Liang* and G S Samudra, "Design of gradient oxide bypassed superjunction power MOSFET devices". IEEE TRANSACTIONS ON POWER ELECTRONICS, 22, no. 4 (2007): 1303 1310. Mahalingam, U, S Rustagi and G S Samudra, "Direct extraction of substrate network parameters for RF MOSFET modeling using a simple test structure". IEEE ELECTRON DEVICE LETTERS, 27, no. 2 (2006): 130 132. Chui*, K J, G S Samudra, Y C Yeo, K C Tee, K W Leong, K M Tee, F Benistant and L Chan, "SDODEL MOSFET for performance enhancement". IEEE ELECTRON DEVICE LETTERS, 26, no. 3 (2005): 205 207. Toh, E H, G H Wang, M ZHU, S Chen, L Chan, G Q Lo, C H Tung, D Sylvester, C H Heng, G S Samudra and Y C Yeo, "Impact Ionization Nanowire Transistor with Multiple Gates, Silicon Germanium Impact Ionization Region, and Sub 5 mV/decade Subtheshold Swing" 195 198 (IEEE International Device Meeting (IEDM) Zhu, Z, T Low, M F Li*, W J Fan, P Bai, D KWONG and G S Samudra, "Modeling study of InSb Thin Film for Advanced III V MOSFET Applications". IEDM 2006 (2006): 807 810. (IEEE International Electron Device Meeting (IEDM 2006) Shen, C, J Q Lin, E H Toh, K F Chang, P Bai, C H Heng, G S Samudra and Y C Yeo, "On the Performance Limit of Impact Ionization Transistors". 117 120 (IEEE International Device Meeting (IEDM),2007
M: Main Supervisor, C: Co supervisor, S: Sole supervisor Koh Shao Ming [M: Yeo Yee Chia], Strained MOSFETs using solid phase epitaxy and other strain inducing methods. M.Eng. Chen Yu (C) [M: Liang Yung C], Superjunction power devices. Oxide bypass and poly flanked lateral power MOSFETs. Ph. D. Chui King Jien (M) [C: Yeo Yee Chia] Performance enhancement of MOSFETs. Source Drain on depletion and Ge condensed strained MOSFETs. Ph. D. 2007 Singh Ravinder Pal (C) [M: Ashwin M. Khambadkone] [C: Liang Yung C] Powering of future microprocessors. Novel circuits. Ph. D. Toh Eng Huat (C) [M: Yeo Yee Chia] Novel IMOS (Impact Ionization MOS). Devices with subthreshold swing below 60mV/Dec for sharp turn off and turn on. Ph. D. Wei Guannan (C) [M: Liang Yung C] SiC based high breakdown voltage devices. M.Eng. Wong Hoong Shing (C) [M: Yeo Yee Chia] Shallow junctions in MOSFETs. Antimony segregation and insito doping methods. Ph. D. Zhao Hui (M) [C: Subhash Rustagi in IME] Simulation of FinFET for RF and scaling. Simulation of scaling with 3D simulations & nanowire device fabrication and characterization. Ph. D. Sreedharan S P (S) Optimization of groove gate MOSFET. Ph. D. 2004 Gan Kian Paau (C) [M: Liang Yung C], Oxide bypass power MOSFETs, M.Eng. 2004 Moitreyee Roy-Mukherjee (S) Lithography resolution enhancement for Cu metallization. Ph. D. 2004 Andrew Khoh (C) [M: Wu Yihong] Optical proximity correction using GTD (Geometrical Theory of Diffraction) for lithography. Ph. D. 2005 Yang Xin (C) [M: Liang Yung C] Tunable VBR power MOSFETs. Tunable oxide bypass power devices. M.Eng. 2004 Lim Chow Yee (C) [M: Liang Yung C] Low forward drop synchronous diode (<< 0.7V). M.Eng. 2004 Naveen Agrawal (S) Simulation and fabrication of Novel MOS. Worked on defining small fins in silicon. M.Eng. 2005 Tee Kian Meng (S) Gate all around MOSFET- simulation and fabrication. M.Eng. 2005 Zhou Kaihong (M) [C: Baiping in IHPC], Simulation of quantum dot memory device mainly for FLASH. M.Eng. 2005 M Umashankar (M) [C: Subhash Rustagi in IME], Characterization and modeling of MOSFETs in RF frequency regime. M.Eng. 2006 Patrick Chan (C) [M: Chor Eng Fong] Inverse modeling for doping profile extraction. M.Eng. 2006 Francis Poh (S) Simulation of 100nm device for logic and memory application. M.Eng. 2002 Tay Chuan Beng (C) [M: Chua Soo Jin] Circuit modeling for SI PIN photodiode. M.Eng. 2002 Lee Siew Weng (S) Predictive process and device simulation of MOSFETs. M.Eng. 2002 Anselm Yip Tze Yieng (S) Simulation of hot carrier effect in MOSFETs. M.Eng. 1999 Zhao Bin (S) An accurate model for BiCMOS/CMOS logic gates. M.Eng. 2000 Wang Yu (M) [C: Ling Chung Ho] Quarter micron process simulation and LDD structure optimization. M.Eng. 1998 Alan Yong Kuen Fatt (S) Analytic methods for timing simulation of interconnects in VLSI integrated circuits. M.Eng. 1997 Lee Teng Kiat (S) Techniques for efficient and accurate simulation of mixed analog and digital circuits. M.Eng. 1995 Seah Boon Pian (C) [M: Ling Chung Ho] Modeling and simulation of hot carrier effects in submicron MOSFETs. M.Eng. 1995 Ali Najafi (C) [M: Farhang] Design of transform domain adaptive filters M.Eng. 1994
EE4415 Integrated Digital Design EE5515 CMOS Front end Processes and Integration